Method for creating circuit redundancy in programmable logic devices
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United States of America Patent
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Feb 25, 2003
Grant Date -
Oct 24, 2002
app pub date -
Apr 13, 2001
filing date -
Apr 13, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate circuits are interrogated by a voting circuit which determines the existence of a faulted circuit in order to eliminate the faulted circuit from the operation of the FPGA. In this manner, without physical addition of redundant circuits, fault tolerancy for the FPGA is provided to minimize the cost, weight, volume, heat and energy associated issues of conventional redundance techniques.
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