Liner materials
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United States of America Patent
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Mar 4, 2003
Grant Date -
N/A
app pub date -
May 23, 2000
filing date -
May 23, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.
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