Integrated compliant probe for wafer level test and burn-in
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United States of America Patent
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Mar 4, 2003
Grant Date -
Sep 19, 2002
app pub date -
Mar 11, 1999
filing date -
Sep 13, 1996
priority date (Note) -
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Abstract
The present invention is directed to a structure comprising a substrate having a surface; a plurality of elongated electrical conductors extending away from the surface; each of said elongated electrical conductors having a first end affixed to the surface and a second end projecting away from the surface; there being a plurality of second ends; and a means for maintaining the plurality of the second ends in substantially fixed positions with respect to each other. The structure is useful as a probe for testing and burning in integrated circuit chips at the wafer level.
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