Wafer testing interposer for a conventional package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Mar 4, 2003
Grant Date -
Jun 20, 2002
app pub date -
Dec 15, 2000
filing date -
Dec 15, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides a wafer interposer for electrical testing and assembly into a conventional package. The present invention provides an interposer comprising a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch than the first electrical terminals, and they are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathway.
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