Circuit with FET transistor pair
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United States of America Patent
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Mar 4, 2003
Issued Date -
N/A
app pub date -
Jun 13, 2002
filing date -
Mar 2, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.
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