US Patent No: 6,529,913

Number of patents in Portfolio can not be more than 2000

Database for electronic design automation applications

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record. Allocation of storage space for data entries may be adaptively managed based on the size of the data to be stored, with allocation size being determined by the largest value of the stored entries, or a header code for the data entry indicating the number of bytes. The data header of each class may include a pointer indicating the position in memory of a main data header, which in turn contains pointers to the positions in memory of the other classes, allowing instances in a class to refer to related instances in the other classes through an integer index number without requiring the use of other pointers.

Loading the Abstract Image... loading....

First Claim

See full text

all claims..

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1572

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Doig, Robert C Campbell, CA 2 379
Scheffer, Louis K Campbell, CA 63 839

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
5,418,961 Parallel tables for data model with inheritance 22 1993
5,519,628 System and method for formulating subsets of a hierarchical circuit design 34 1993
5,761,664 Hierarchical data model for design automation 29 1993
6,360,350 Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms 18 1997
 
CADENCE DESIGN SYSTEMS, INC. (3)
5,838,583 Optimized placement and routing of datapaths 211 1996
5,864,838 System and method for reordering lookup table entries when table address bits are reordered 4 1996
5,883,811 Method for electric leaf cell circuit placement and timing determination 11 1997
 
BUCKWOLD, LIA (1)
5,247,666 Data management method for representing hierarchical functional dependencies 38 1991
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,267,175 Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design 69 1993
 
LSI LOGIC CORPORATION (1)
6,135,647 System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code 42 1997
 
SYNOPSYS, INC. (1)
6,152,612 System and method for system level and circuit level modeling and design simulation using C++ 83 1997
 
VLSI TECHNOLOGY, INC. (1)
5,487,018 Electronic design automation apparatus and method utilizing a physical information database 39 1993

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (3)
7,168,041 Method and apparatus for table and HDL based design entry 28 2002
7,058,916 Method for automatically sizing and biasing circuits by means of a database 3 2002
7,543,262 Analog layout module generator and method 54 2005
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
7,047,511 Electronic circuit design 3 2003
8,626,713 Multiple contexts in a redirect on write file system 0 2010
8,396,832 Independent fileset generations in a clustered redirect-on-write filesystem 0 2010
 
AGERE SYSTEMS INC. (1)
7,340,697 Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies 2 2004
 
ALTERA CORPORATION (1)
8,516,504 Method for adding device information by extending an application programming interface 0 2003
 
FACTIVA, INC. (1)
7,908,253 Polyarchical data indexing and automatically generated hierarchical data indexing paths 0 2008
 
FUJI JUKOGYO KABUSHIKI KAISHA (1)
6,938,046 Polyarchical data indexing and automatically generated hierarchical data indexing paths 35 2001
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
6,801,884 Method and apparatus for traversing net connectivity through design hierarchy 10 2001
 
LSI CORPORATION (1)
7,480,650 NQL—netlist query language 1 2007
 
LSI LOGIC CORPORATION (1)
7,283,995 NQL--netlist query language 1 2004
 
MICROSOFT CORPORATION (1)
8,266,172 Data parallel query analysis 0 2009
 
NXP B.V. (1)
7,024,640 Integrated circuit cell identification 8 2001
 
R3 LOGIC, INC. (1)
8,266,560 Methods and systems for computer aided design of 3D integrated circuits 2 2011
 
SYNOPSYS, INC. (1)
8,549,461 Generation of independent logical and physical hierarchy 1 2011
 
XILINX, INC. (1)
7,536,377 Component naming 4 2003

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Sep 4, 2014
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00