
US Patent No: 6,529,913
Number of patents in Portfolio can not be more than 2000
Database for electronic design automation applications
Stats
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Mar 4, 2003
Issued date -
Oct 11, 2000
filing date -
09/689,167
serial no -
In Force
status
Importance
Abstract
A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record. Allocation of storage space for data entries may be adaptively managed based on the size of the data to be stored, with allocation size being determined by the largest value of the stored entries, or a header code for the data entry indicating the number of bytes. The data header of each class may include a pointer indicating the position in memory of a main data header, which in turn contains pointers to the positions in memory of the other classes, allowing instances in a class to refer to related instances in the other classes through an integer index number without requiring the use of other pointers.
First Claim
Related Publications
International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,418,961 Parallel tables for data model with inheritance | 19 | 1993 | |
| 5,519,628 System and method for formulating subsets of a hierarchical circuit design | 34 | 1993 | |
| 5,761,664 Hierarchical data model for design automation | 27 | 1993 | |
| 6,360,350 Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms | 12 | 1997 | |
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| 5,838,583 Optimized placement and routing of datapaths | 195 | 1996 | |
| 5,864,838 System and method for reordering lookup table entries when table address bits are reordered | 4 | 1996 | |
| 5,883,811 Method for electric leaf cell circuit placement and timing determination | 11 | 1997 | |
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| 5,247,666 Data management method for representing hierarchical functional dependencies | 37 | 1991 | |
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| 5,267,175 Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design | 68 | 1993 | |
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| 6,135,647 System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code | 41 | 1997 | |
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| 6,152,612 System and method for system level and circuit level modeling and design simulation using C++ | 72 | 1997 | |
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| 5,487,018 Electronic design automation apparatus and method utilizing a physical information database | 39 | 1993 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 4, 2014 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |