Write data error checking in a PCI Bus system
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United States of America Patent
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Mar 4, 2003
Grant Date -
N/A
app pub date -
Mar 9, 2000
filing date -
Mar 9, 2000
priority date (Note) -
Expired
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Abstract
In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| INTERNATIONAL BUSINESS MACHINES CORPORATION | NEW ORCHARD ROAD ARMONK NY 10504 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Beardsley, Brent Cameron | Tucson, AZ | 49 | 2484 |
| Benhase, Michael Thomas | Tucson, AZ | 90 | 2222 |
| Lucas, Gregg Steven | Tucson, AZ | 58 | 605 |
| Yanes, Juan Antonio | Tucson, AZ | 14 | 122 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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