Method of constraining non-uniform layouts using a uniform coordinate system
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United States of America Patent
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Mar 4, 2003
Grant Date -
Nov 28, 2002
app pub date -
Mar 29, 2001
filing date -
Mar 29, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A method of designating circuit element positions using uniform coordinate systems that can be applied to non-uniform logic arrays. A 'site map' is constructed comprising a uniform array of 'sites'. A uniform coordinate system is applied to the site map. The various logic blocks, which may be of different types and sizes, are mapped to the site array. The result is the imposition of a uniform coordinate system on a non-uniform logic array, using the intervening abstraction of a site array. Because the site array is uniform, a relative location constraint applied to a site within the site array retains its validity regardless of the location of the site within the site array, even when the relative location constraints are normalized.
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