Flip-flop with metastability reduction
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United States of America Patent
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Mar 11, 2003
Grant Date -
N/A
app pub date -
Dec 19, 2001
filing date -
Dec 19, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A flip-flop circuit with metastability reduction having two internal flip-flops connected in a parallel configuration relative to an input line with a input data delay connected to the data input of one of the flip-flops. The outputs are combined and since at least one of the flip-flop outputs should be stable, if the output of one of the flip-flop goes into a metastable state, the output of the other flip-flop will stabilize it, thus producing a stable output.
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