Computer system for dynamically scaling busses during operation
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United States of America Patent
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Mar 11, 2003
Issued Date -
N/A
app pub date -
Mar 15, 2002
filing date -
Feb 12, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.
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