Method for reducing base to collector capacitance and related structure

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United States of America Patent

PATENT NO 6534802
SERIAL NO

09850028

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Abstract

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According to a disclosed embodiment, a transistor region comprising a collector region is opened adjacent to an oxide region. The oxide region may be, for example, a field oxide region. Additionally, an extrinsic collector region is formed under the oxide region. A blanket layer of dielectric is deposited over the transistor region and the oxide region. The blanket layer of dielectric can comprise, for example, silicon dioxide. The blanket layer of dielectric is etched away from the transistor region, leaving behind a dielectric segment on the oxide region. Following, a base region comprising, for example, single-crystal silicon-germanium, is grown over the collector region. Concurrently, a conductive region that is electrically connected to the base region is formed over the oxide region. The dielectric segment on the oxide region increases the separation between the conductive region and the extrinsic collector region, thus lowering the base to collector capacitance.

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Patent Owner(s)

Patent OwnerAddress
NEWPORT FAB LLC4311 JAMBOREE ROAD NEWPORT BEACH CA 92660-3095

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schuegraf, Klaus F Aliso Viejo, CA 59 1349

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