Test and observe mode for embedded memory
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United States of America Patent
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Mar 18, 2003
Grant Date -
N/A
app pub date -
Jul 13, 1999
filing date -
Jul 13, 1999
priority date (Note) -
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Abstract
A method and apparatus that tests and observes how an embedded DRAM is being accessed by a logic circuit controlling the DRAM is provided. The test and observe method and apparatus pipes the outputs of the logic, which is used as inputs to the embedded DRAM, to an observation device. The outputs of the logic device are then observed at the observation device to determine how the DRAM is being accessed. In addition, information concerning what data is being trapped and when may be output to the observation device to determine setup and hold times for the DRAM.
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