TSOP memory chip housing configuration
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United States of America Patent
Stats
-
Mar 25, 2003
Grant Date -
Jan 16, 2003
app pub date -
Jan 15, 2002
filing date -
Jul 15, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory chip with a number of pins disposed in an interior of the TSOP memory chip housing. The pins leading out of a respective TSOP memory chip housing and, via a rewiring configuration, are connected to pins leading out of a respectively directly adjacent TSOP memory chip housing of the same TSOP memory chip housing stack. In order to be able to produce such a housing stack as cost-effectively and simply as possible by an automated mounting method, the rewiring configuration is implemented in the form of leadframes respectively disposed between or at the side between the individual TSOP memory chip housings.
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