Method and apparatus for identifying instructions for performance monitoring in a microprocessor
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United States of America Patent
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Mar 25, 2003
Grant Date -
N/A
app pub date -
Nov 8, 1999
filing date -
Nov 8, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.
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