Low voltage planar power MOSFET with serpentine gate pattern
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United States of America Patent
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Apr 1, 2003
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N/A
app pub date -
Mar 28, 2000
filing date -
Mar 28, 2000
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Abstract
A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.
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