Nonvolatile programmable logic devices
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United States of America Patent
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Apr 1, 2003
Grant Date -
N/A
app pub date -
Jul 28, 2000
filing date -
Jul 30, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.
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