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Abstract

A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers. Also provided is a coprocessor of the type that includes a series input terminal, a series output terminal, and computation elements located on at least one data path between the series input terminal and the series output terminal. Further, an IC chip card that includes a microprocessor, storage, and a coprocessor is provided.

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First Claim