Method for in-line testing of flip-chip semiconductor assemblies

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6545498
APP PUB NO 20010043077A1
SERIAL NO

09819472

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using 'wet' quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using 'dry' epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cobbley, Chad A Boise, ID 127 2220
Jiang, Tongbi Boise, ID 331 5995
Street, Bret K Meridian, ID 94 536
VanNortwick, John Kuna, ID 36 199

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation