Nonvolatile semiconductor memory device
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United States of America Patent
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Apr 8, 2003
Grant Date -
Jul 25, 2002
app pub date -
Mar 11, 2002
filing date -
Mar 18, 1996
priority date (Note) -
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Abstract
A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
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