Detector error suppression circuit and method
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United States of America Patent
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Apr 8, 2003
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N/A
app pub date -
Apr 14, 2000
filing date -
May 19, 1999
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Abstract
Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1-D)(1+D).sup.3 to the detected EPR4 bits.
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