Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program

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United States of America Patent

PATENT NO 6546540
SERIAL NO

09713050

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Abstract

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With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Igarashi, Mutsunori Kanagawa-ken, JP 23 1448
Ishioka, Takashi Kanagawa-ken, JP 14 198
Minami, Fumihiro Kanagawa-ken, JP 34 1191
Mitsuhashi, Takashi Kanagawa-ken, JP 48 1549
Murakata, Masami Kanagawa-ken, JP 12 830
Yamada, Masaaki Kanagawa-ken, JP 99 2190

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