Field effect transistor with reduced narrow channel effect
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United States of America Patent
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-
Apr 15, 2003
Grant Date -
Mar 7, 2002
app pub date -
Jun 12, 2001
filing date -
Dec 7, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain regions are formed on the major surface of the element region to oppose via a channel region under the gate electrode. The channel region has a main portion having an upper surface at a level higher than the upper end portion of a trench side wall, and a side portion having an upper surface tilting downward from the main portion to the upper end portion of the trench side wall. The dopant impurity in the channel region has a concentration peak located at a level lower than the upper end portion of the trench side wall. The distance from the upper surface of the main portion to the concentration peak is larger than that from the upper surface of the side portion to the peak.
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