Apparatus and method for analyzing functional failures in integrated circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 15, 2003
Grant Date -
N/A
app pub date -
Jun 2, 2000
filing date -
Jun 2, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus and method are presented for identifying and mapping functional failures in an integrated circuit (IC) due to timing errors therein based on the generation of functional failures in the IC. This is done by providing a set of input test vectors to the IC and adjusting one or more: of the IC voltage, temperature or clock frequency; the rate at which the test vectors are provided to the IC; or the power level of a focused laser beam used to probe the IC and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures. The present invention has applications for optimizing the design and fabrication of ICs, for failure analysis, and for qualification or validation testing of ICs.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully