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Abstract

An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.

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First Claim