Using multiple status bits per cell for handling power failures during write operations
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United States of America Patent
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Apr 15, 2003
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N/A
app pub date -
Feb 15, 2002
filing date -
Feb 15, 2002
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Abstract
A multi-level cell memory may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.
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