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Abstract

It is disclosed an algorithm able to compress a defined set of addresses S, the set of addresses to be compressed, belonging to the set U, the whole addressing space; for each of these addresses the algorithm must identify one and only one address belonging to C, the set of compressed address (i.e. perform a transformation S.fwdarw.C). The algorithm may be implemented using some low-cost random access memories (RAM) and some control logic. A performance comparison shows that is possible to perform the address compression using one order of magnitude less memory respect to the state-of-the-art techniques. Basically, the method of the invention combines the splitting of the incoming address space (U) into a plurality of sub-spaces, a tree search algorithm for clustering a defined set (S) of identifiers contained in the sub-spaces into which the incoming addresses space (U) has been split and a sequential search performed within the right cluster in order to identify the compressed address belonging to space C. The patent covers the algorithm, a preferred embodiment and some extended embodiments, that give extra gain. Thanks to the invention is thus possible to implement silicon devices able to compress one order of magnitude more managed channels with respect to the state-of-the-art techniques, without area changes. Conversely, it is possible to implement the address compression function with one order magnitude less memory resources with respect to the state-of-the-art techniques.

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First Claim