Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address
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United States of America Patent
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Apr 15, 2003
Issued Date -
N/A
app pub date -
Nov 16, 2000
filing date -
Jul 13, 1998
priority date (Note) -
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Abstract
An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.
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