System and method of monitoring a distributed fault tolerant computer system
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United States of America Patent
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Apr 15, 2003
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N/A
app pub date -
Jun 29, 1999
filing date -
Jun 29, 1999
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Abstract
A system and method for monitoring a distributed fault tolerant computer system. A hardware counter mechanism (e.g. a countdown counter) is reset repeatedly by a software reset mechanism during normal operation, thereby preventing the counter mechanism from reaching a count indicative of the existence of a fault. A unit provides a signal to a bus indicative of the status (ON or OFF) of the unit. A management subsystem defines a configuration for the distributed fault tolerant computer system. The management subsystem is responsive to status signals on the bus and selectively reconfigures a stored representation in response to changing status signals on the bus.
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