T-Ram array having a planar cell structure and method for fabricating the same
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United States of America Patent
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Apr 22, 2003
Grant Date -
Jul 18, 2002
app pub date -
Jan 16, 2001
filing date -
Jan 16, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F.sup.2 for a prior art T-RAM cell to a cell size of less than or equal to 6F.sup.2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.
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