Technique to reduce reflections and ringing on CMOS interconnections
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 22, 2003
Grant Date -
N/A
app pub date -
Aug 30, 1999
filing date -
Aug 30, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention provides a method and apparatus, for integrated circuit or printed circuit board interconnections, which is able to minimize the reflections and ringing with minimal delay of signals which are propagated through transmission lines to destination points within the circuit or board. The invention utilizes interconnection lines which are designed to have a resistivity, line length, and line cross sectional area which produces a resistance of the interconnection line which will minimize the ringing and reflections with minimal delay of the signal propagated to the destination points to insure signal quality.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully