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United States of America Patent
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Apr 22, 2003
Issued Date -
N/A
app pub date -
Jul 31, 2000
filing date -
Jul 9, 1999
priority date (Note) -
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Abstract
Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.
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