Programmable element latch circuit
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United States of America Patent
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Apr 22, 2003
Grant Date -
N/A
app pub date -
Aug 18, 2000
filing date -
Aug 18, 2000
priority date (Note) -
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status (Latency Note)
Importance
Abstract
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.
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