Semiconductor chip having pads with plural junctions for different assembly methods
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United States of America Patent
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-
Apr 29, 2003
Grant Date -
Jun 6, 2002
app pub date -
Jan 9, 2002
filing date -
Sep 11, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.
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