Method and apparatus for using parasitic effects in processing high speed signals

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United States of America Patent

PATENT NO 6556056
SERIAL NO

10118733

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Abstract

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A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Silicon On Insulator (SOI) CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another SOI CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting drastic improvement of output signal ripple is also graphically presented.

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Patent Owner(s)

Patent OwnerAddress
QANTEC COMMUNICATIONS INCSUITE 240 20370 TOWN CENTER LANE CUPERTINO CA 95014

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tung, John C Cupertino, CA 12 66
Zhang, Minghao(Mary) Cupertino, CA 8 28

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