Ferroelectric and high dielectric constant transistors
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United States of America Patent
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May 6, 2003
Issued Date -
N/A
app pub date -
Oct 11, 2000
filing date -
Oct 23, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated circuit includes a layered superlattice material having the formula A1.sub.w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+sk B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
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