Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
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United States of America Patent
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May 6, 2003
Grant Date -
Nov 28, 2002
app pub date -
Jul 29, 2002
filing date -
Mar 1, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
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