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Abstract

A power line communication system includes a field-programmable gate array (FPGA) having a sine wave approximator driven by a high frequency clock in the FPGA. The sine wave approximator generates a high frequency sine wave-shaped communication signal on command by a processor. The data transmission scheme includes sending a sequence of fixed length and fixed frequency cells wherein each transmitted cell is of one of four phases 0.degree., 90.degree., 180.degree. or 270.degree. (FIG. 2) relative to the phase of a preceding transmitted cell with the first transmitted cell designated as a zero-phase reference cell. The data transmissions are synchronized by the voltage zero crossings of the AC power line and each transmission consists of 27 cells evenly distributed over the AC voltage line half cycle. The high frequency sine wave-shaped communication signal is superimposed on the low frequency (60 Hz) AC power line via a transconductance amplifier which draws current from the AC power line via a full-wave bridge rectifier. The resulting signal is passed through several stages of filtering and then quantized by a digitizing comparator. The quantized output is a 1-bit in phase or 90 degree out of phase signal which is fed to a demodulator unit within the FPGA. The demodulator unit includes a quadrature generator and two digital integrators for detecting the phase of the incoming signal. The demodulated signal is sent back to the processor for communication data recognition.

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