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Abstract

An apparatus and method are presented for programmable built-in self-test (BIST) and built-in self-repair (BISR) of an embedded memory (i.e., a memory formed with random logic upon a semiconductor substrate). A semiconductor device may include a memory unit, a BIST logic unit coupled to the memory unit, and a master test unit coupled to the BIST logic unit and the memory unit. The memory unit stores data input signals in response to a first set of address and control signals, and provides the stored data input signals as data output signals in response to a second set of address and control signals. The master test unit provides the memory test pattern to the BIST logic unit and generates the first and second sets of address and control signals. The BIST logic unit stores the memory test pattern, produces the data input signals dependent upon the memory test pattern, provides the data input signals to the memory unit, receives the data output signals from the memory unit, and compares the data output signals to the data input signals to form BIST results. The BIST system may perform a hardwired BIST routine when an asserted RESET signal is received by the semiconductor device and/or a programmable BIST routine under software control. The BIST logic unit may include a redundant memory structure, and may be configured to functionally replace a defective memory structure of the memory unit with one of the redundant memory structures dependent upon the BIST results.

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