Semiconductor memory device
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United States of America Patent
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May 13, 2003
Grant Date -
Jan 10, 2002
app pub date -
Jun 4, 2001
filing date -
Jul 4, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).
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