Synchronous interface for a nonvolatile memory
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United States of America Patent
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May 13, 2003
Issued Date -
N/A
app pub date -
Jun 14, 2000
filing date -
Jun 3, 1994
priority date (Note) -
Expired
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Importance
Abstract
A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.
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