US Patent No: 6,566,904

Number of patents in Portfolio can not be more than 2000

Pad calibration circuit with on-chip resistor

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ALSO PUBLISHED AS: 20020163355
ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

A pad calibration circuit with on-chip resistor. An integrated circuit with an impedance terminated output terminal is disclosed. A source is provided for sourcing current to the output terminal of the integrated circuit, which output terminal interfaces with a load having a finite impedance associated therewith. An on-chip source impedance is disposed internal to the integrated circuit and between the source and the output terminal to define the input impedance of the output terminal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
VITESSE SEMICONDUCTOR CORPORATIONCAMARILLO, CA98

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Katikaneni, Pradeep Austin, TX 3 45
van, Bavel Nicholas Austin, TX 6 96

Cited Art

Patent Info (Count) # Cites Year
 
AT&T Bell Laboratories (3)
5,194,765 Digitally controlled element sizing 199 1991
5,243,229 Digitally controlled element sizing 20 1991
5,298,800 Digitally controlled element sizing 46 1992
 
INTEL CORPORATION (1)
6,380,758 Impedance control for wide range loaded signals using distributed methodology 38 2000
 
KABUSHIKI KAISHA TOSHIBA (1)
6,127,862 Programmable impedance circuit 18 1998
 
SUN MICROSYSTEMS, INC. (1)
5,955,894 Method for controlling the impedance of a driver circuit 44 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
BROADCOM CORPORATION (3)
7,301,365 On-chip source termination in communication systems 3 2005
7,576,587 On-chip source termination in communication systems 1 2007
7,884,639 On-chip source termination in communication systems 0 2009
 
SAMSUNG ELECTRONICS CO., LTD. (2)
6,768,393 Circuit and method for calibrating resistors for active termination resistance, and memory chip having the circuit 15 2002
7,786,752 Memory systems, on-die termination (ODT) circuits, and method of ODT control 3 2007
 
GOOGLE INC. (1)
6,718,420 Phase manipulation of intertwined bus signals for reduction of hostile coupling in integrated circuit interconnects 0 2001
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,737,894 Method and apparatus for generating impedance matched output signals for an integrated circuit device 2 2003
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
7,332,904 On-chip resistor calibration apparatus and method 4 2005
 
QIMONDA AG (1)
6,946,848 Calibration configuration 6 2003
 
STMICROELECTRONICS PVT. LTD. (1)
6,856,179 CMOS buffer with reduced ground bounce 3 2003
 
VITESSE SEMICONDUCTOR CORPORATION (1)
7,817,674 Output clock adjustment for a digital I/O between physical layer device and media access controller 0 2004

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Nov 20, 2014
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Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00