Method and apparatus for programming multi-state cells in a memory device
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United States of America Patent
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May 20, 2003
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app pub date -
Jun 19, 2001
filing date -
Dec 29, 1998
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Abstract
A method for programming multi-state floating gate transistor memory cells, also called multi-state flash cells, in a memory system is disclosed. The memory system includes control circuitry for controlling an array of multi-state flash cells which are arranged in blocks and connected together in rows and columns. The method is implemented as a series of programmable instructions stored and implemented in the memory system. According to the method groups of multi-state flash cells are incrementaly programmed. In each programming step the threshold voltage levels of the cells being programmed is raised only one state. Successive subgroups of cells are programmed to increase their threshold voltage levels in a step-by-step manner. The multi-state flash cells are programmed to store the desired data over several steps. Cells that are under-programmed in any step are reprogrammed before the method continues. Margins between the threshold voltage levels in the cells are maintained by a verification of the programmed cells. Over-programmed multi-state flash cells are identified and discarded at each programming step by calculating and retaining overshoot data.
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