Apparatus and method for system access to tap controlled BIST of random access memory
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United States of America Patent
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May 20, 2003
Grant Date -
N/A
app pub date -
Apr 9, 2001
filing date -
Apr 9, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit having functional logic that provides system access to test access port controlled built-in-self-test logic is provided. The integrated circuit includes a test access port controller having an enable output and a status input. A built-in-self-test controller having an enable input, a status output, one or more random access memory cell controller outputs and one or more random access memory cell inputs is also provided. A functional logic interface is connected to the functional logic, the test access port controller enable output, and the built-in-self-test controller enable input, and allows a built-in self-testing sequence to be initiated from the test access port controller or the system.
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