Method for designing large standard-cell base integrated circuits
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United States of America Patent
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May 20, 2003
Grant Date -
Jul 4, 2002
app pub date -
Jun 4, 2001
filing date -
Sep 6, 2000
priority date (Note) -
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Abstract
An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.
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