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Abstract

An interface card for a network or other communication channel, with limited intelligence, is implemented using a relatively slower, and lower cost embedded processor, supported by dedicated hardware logic for the purposes of intercepting certain packets being received via the network or communication channel. The interface comprises the first port on which incoming data is received at the data transfer rate of the network, a buffer coupled to the port that stores received packets, and a second port coupled with the buffer through which transfer of packets to the host is executed. Packet filters are coupled to the first port which identifies packets being stored in the buffer that have one of the plurality of variant formats. A processor is coupled with the buffer as well, and is responsive to the packet filter to process identified packets in the buffer. The pattern match logic includes mask logic circuits, circuits to generate a hash in response to bytes selected by the mask, and a comparator which compares the output of the hash logic with an expected hash. If a match is detected, then the processor is signaled that the packet being received is, or may be, suitable for processing on the network interface card. The mask logic uses the mask modifier in response to the packet format, so that variations of a particular format can be handled with a single set of pattern match logic circuits.

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First Claim