Method and apparatus for logic synthesis (word oriented netlist)
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 3, 2003
Grant Date -
N/A
app pub date -
Aug 16, 1999
filing date -
Aug 16, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully