Security card and a computer system provided with an interface for reading a security card

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United States of America Patent

PATENT NO 6575373
SERIAL NO

09662864

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Abstract

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A security card 20 including a CPU 1 for executing instruction sequences such as a password verifying routine, a memory 2 configured to store secret data such as the password and so forth, a random signal generation circuit 4 configured to generate a wait signal which is output in order to halt the operation of the CPU 1. When the wait signal is input, the CPU 1 halts its operation for a short time such as one to several clocks. In accordance with the security card 20, the operation of the CPU 1 can be deferred for a short time in an arbitrary timing in order to make it difficult to analyze the operation of the CPU 1.

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Patent Owner(s)

  • KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nakano, Hiroo Kanagawa-ken, JP 15 141

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