Importance

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Abstract

A system and method for determining link capacity utilization for High Level Data Link Control (HDLC) encoded links is presented. The links transport frames comprised of a known number of bits during a time period and the frames comprise variable length data packets and uniform length sync flags. A circuit, which aids in determining the link capacity utilization, includes a flag detector, a counter, a timeout register, and a shadow register. A sync flag count state is entered if a sync flag is detected by the flag detector. The counter is then incremented if a repeated sync flag is detected within a next data byte. When the time period expires the number of repeated sync flags are forwarded to the shadow register. A processor and the timeout register, which are coupled to the counter, respectively access the number of repeated sync flags and reset the counter. The processor then calculates the link capacity utilization.

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First Claim