Transistor level circuit simulator using hierarchical data
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United States of America Patent
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Jun 10, 2003
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app pub date -
May 7, 1999
filing date -
May 7, 1999
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Abstract
Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state. Selected ones of the subcircuits in each of the plurality of subsets share a same dynamic voltage state, where memory storage for the same dynamic voltage state is shared by the subcircuits in each of the selected ones of the plurality of subsets. Once generated, the hierarchical representation may be used during simulation of the circuit to reduce the number of computations required.
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