Structure and method for fabrication of a leadless chip carrier with embedded antenna
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Jun 24, 2003
Issued Date -
N/A
app pub date -
Jul 26, 2001
filing date -
Nov 15, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A substrate has a top surface for receiving a semiconductor die. An antenna is patterned on the bottom surface of the substrate. The antenna is accessible by coupling it to a via and, through the via, to a substrate signal bond pad and a semiconductor die signal bond pad. In one embodiment, there is at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a substrate bond pad and the printed circuit board. The at least one via also provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.
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